1. Field of the Invention
The present invention relates to a semiconductor chip and a manufacturing method thereof, and more particularly, to a semiconductor chip, which has an alignment mark formed on the surface of the semiconductor chip where no external connection bump is formed and has the position information of the external connection bump, and to a method of manufacturing the same.
2. Description of the Related Art
Recently, the development of a printed circuit board (PCB) including a semiconductor chip is receiving attention as next-generation packaging technology for multi-functionalization and miniaturization.
The PCB including the semiconductor chip is advantageous in terms of high functionality, as well as multi-functionalization and miniaturization, and thereby solves problems related to decreased reliability in the course of making the electrical connection of the semiconductor chip using a wire bonding or solder ball for a flip chip or a BGA (ball grid array).
FIGS. 1A and 1B show the process of manufacturing a PCB including a semiconductor chip according to a conventional technique. With reference to these drawings, the problems of the conventional technique are described below.
As shown in FIG. 1A, a substrate body 10 including an insulating layer 13 having a cavity 20, in which a semiconductor chip 30 is to be mounted, and the semiconductor chip 30, disposed above the cavity 20, are provided. The semiconductor chip 30 is transferred in a state of being attached to a header, which is not shown, using a vacuum adsorption mechanism, and is thus mounted in the substrate body 10. After the semiconductor chip 30 is mounted, an insulating layer 70 is formed on the substrate body 10, and a circuit layer 90, including a circuit pattern 91 and a via 93 electrically connected with the connection pad 33 provided on one surface of the semiconductor chip 30, is then formed on the insulating layer 70, thus manufacturing the PCB including the semiconductor chip 30.
However, because the connection pad 33 of the semiconductor chip 30 is not externally observable due to the insulating layer 70 formed on the substrate body 10, it is difficult to determine the position of the via hole which is formed in the insulating layer 70 to expose the connection pad 33.
In order to maintain the position matching of the connection pad 33 and the via 93, the semiconductor chip 30 must be mounted in a state of being aligned with respect to a predetermined alignment standard. Conventionally, as shown in FIG. 1A, a detector 60 disposed between the substrate body 10 and the semiconductor chip 30 is used to detect the position of the circuit pattern 15 formed on the substrate body 10 and the position of the connection pad 33 of the semiconductor chip 30, and thus, the semiconductor chip 30 is mounted so that the position of the connection pad 33 is aligned with respect to the circuit pattern 15 formed on the substrate body 10.
However, the connection pad 33 is located not toward the circuit pattern 15 formed on the upper surface of the substrate body 10 but toward a circuit pattern 17 formed on the lower surface of the substrate body 10. Although the circuit pattern 15 formed on the upper surface of the substrate body 10 and the circuit pattern 17 formed on the lower surface of the substrate body 10 are formed to fulfill a predetermined matching requirement in order to realize interlayer connection, the circuit patterns 15, 17 formed on the upper and lower surfaces of the substrate body are not completely matched, attributable to an error in the process of exposing a photosensitive resist. So, the case where the semiconductor chip 30 is mounted based on the circuit pattern 15 formed on the substrate body 10 is problematic in that the connection pad 33 of the semiconductor chip 30 is not matched with the via 93 in the circuit layer 90 formed on the insulating layer 70, as shown in FIG. 1B.
Further, similar problems are caused even in a face-up mounting process, as well as a face-down mounting process. Specifically, in the case where the semiconductor chip is mounted through a face-up process, it is impossible to detect the position of the connection pad of the semiconductor chip by the header for transferring the semiconductor chip. Thus, in the face-up mounting process, the semiconductor chip is disposed based on the external shape of the semiconductor chip and the upper circuit pattern of the substrate body. However, in the case of the semiconductor chip, it does not have a predetermined external shape due to an error in the dicing process. Hence, the case where the semiconductor chip is mounted based on the external shape thereof incurs problems in which the position of the connection pad is not matched with the via hole of the external circuit layer.
Therefore, the semiconductor chip having a structure able to match the via 93 formed outside the substrate body 10 with the connection pad 33 of the semiconductor chip 30 and a method of manufacturing the same are required.